SH7125_08 Datasheet, PDF (429/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

WTCNT value
H'FF
Section 11 Watchdog Timer (WDT)
Overflow occurs
H'00
WT/IT = 1
TME = 1
WDTOVF signal
Time
H'00 is written
to WTCNT
WOVF = 1
WDTOVF is asserted and
an internal reset is generated
H'00 is written
to WTCNT
Count starts
Internal reset signal
(power-on reset selected)
32 Pφ clock
3 Pφ + one cycle of count clock
Internal reset signal
(manual reset selected)
18 Pφ clock
Figure 11.3 Operation in Watchdog Timer Mode
(When WTCNT Count Clock is Specified to Pφ/32 by CKS2 to CKS0)
11.4.3 Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and
set the initial value of the counter in the WTCNT counter.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval
timer interrupt request is sent to the INTC. The counter then resumes counting.
Rev. 4.00 Jul. 25, 2008 Page 409 of 750
REJ09B0243-0400