SH7125_08 Datasheet, PDF (277/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.4.6 Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits
CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of
TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs
when TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is
counting up or down.
Table 9.47 shows the correspondence between external clock pins and channels.
Table 9.47 Phase Counting Mode Clock Input Pins
Channels
When channel 1 is set to phase counting mode
When channel 2 is set to phase counting mode
External Clock Pins
A-Phase
B-Phase
TCLKA
TCLKB
TCLKC
TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 9.29 shows an example of the
phase counting mode setting procedure.
Phase counting mode
Select phase counting [1]
mode
[1] Select phase counting mode with bits
MD3 to MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start
the count operation.
Start count
[2]
<Phase counting mode>
Figure 9.29 Example of Phase Counting Mode Setting Procedure
Rev. 4.00 Jul. 25, 2008 Page 257 of 750
REJ09B0243-0400