SH7125_08 Datasheet, PDF (761/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Table 5.6 Bus Cycles and
Address Errors
Page Revision (See Manual for Details)
77 Deleted
Bus Cycle
Type
Bus
Master
Instruction CPU
fetch
Data
CPU
read/write
Bus Cycle Description Address Errors
Instruction fetched from Address error
on-chip peripheral
occurs
module space
Instruction fetched from Address error
external memory space occurs
in single chip mode
Word data accessed
from even address
None (normal)
Longword data
accessed in 8-bit on-
chip peripheral module
space
None (normal)
Reserved space
accessed when in
single chip mode
Address error
occurs
Table 8.1 Address Map
147
Amended
Address
H'00020000 to
H'FFFF9FFF
H'84000000 to
H'84007FFF
H'84008000 to
H'8400FFFF
H'84010000 to
H'8401FFFF
H'84020000 to
H'FFFF9FFF
H'FFFFA000 to
H'FFFFBFFF
H'FFFFC000 to
H'FFFFFFFF
Type of Memory
Reserved
Size
128 Kbytes 64 Kbytes
Version
Version
—
—
32 Kbytes
Version
—
Bus Width
—
On-chip FLASH
128 Kbytes 64 Kbytes 32 Kbytes 8
programming area
Reserved
Reserved
Reserved
—
—
—
—
On-chip RAM
8 Kbytes 8 Kbytes 8 Kbytes 32
On-chip peripheral 128 Kbytes 64 Kbytes 64 Kbytes 8/16
I/O
Figure 9.64 Example of Output 297
Phase Switching by External
Input (2)
Figure 9.66 Example of Output 299
Phase Switching by Means of UF,
VF, WF Bit Settings (2)
Amended
Output waveform of the terminal amended.
Amended
Output waveform of the terminal amended.
Rev. 4.00 Jul. 25, 2008 Page 741 of 750
REJ09B0243-0400