SH7125_08 Datasheet, PDF (501/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Initial
Bit
Bit Name Value
8
STC
0
7, 6 CKSL[1:0] 00
5, 4 ADM[1:0] 00
3
ADCS
0
Section 13 A/D Converter (ADC)
R/W Description
R/W State Control
Sets the A/D conversion time in combination with the
CKSL1 and CKSL0 bits.
0: 50 states
1: 64 states
When changing the A/D conversion time, first clear the
ADST bit to 0.
R/W Clock Select 1 and 0
Select the A/D conversion time.
00: Pφ/4
01: Pφ/3
10: Pφ/2
11: Pφ
When changing the A/D conversion time, first clear the
ADST bit to 0.
CKSL[1:0] = B'11 can be set while Pφ ≤ 25 MHz.
R/W A/D Mode 1 and 0
Select the A/D conversion mode.
00: Single mode
01: 4-channel scan mode
10: Setting prohibited
11: 2-channel scan mode
When changing the operating mode, first clear the
ADST bit to 0.
R/W A/D Continuous Scan
Selects either single-cycle scan or continuous scan in
scan mode. This bit is valid only when scan mode is
selected.
0: Single-cycle scan
1: Continuous scan
When changing the operating mode, first clear the
ADST bit to 0.
Rev. 4.00 Jul. 25, 2008 Page 481 of 750
REJ09B0243-0400