SH7125_08 Datasheet, PDF (447/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
Initial
Bit
Bit Name value R/W Description
2
TEND
1
R
Transmit End
Indicates that no valid data was in SCTDR during
transmission of the last bit of the transmit character
and transmission has ended.
The TEND flag is read-only and cannot be modified.
0: Indicates that transmission is in progress
[Clearing condition]
• When 0 is written to TDRE after reading TDRE = 1
1: Indicates that transmission has ended
[Setting conditions]
• By a power-on reset or in standby mode
• When the TE bit in SCSCR is 0
• When TDRE = 1 during transmission of the last bit
of a 1-byte serial transmit character
1
MPB
0
R
Multiprocessor Bit
Stores the multiprocessor bit found in the receive
data. When the RE bit in SCSCR is cleared to 0, its
previous state is retained.
0
MPBT
0
R/W Multiprocessor Bit Transfer
Specifies the multiprocessor bit value to be added to
the transmit frame.
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 4.00 Jul. 25, 2008 Page 427 of 750
REJ09B0243-0400