SH7125_08 Datasheet, PDF (358/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.7.9 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input
capture transfer for channel 5.
Figures 9.113 and 9.114 show the timing in this case.
TGR read cycle
T1 T2
MPφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
N
Figure 9.113 Contention between TGR Read and Input Capture (Channels 0 to 4)
TGR read cycle
T1 T2
MPφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
M
Figure 9.114 Contention between TGR Read and Input Capture (Channel 5)
Rev. 4.00 Jul. 25, 2008 Page 338 of 750
REJ09B0243-0400