SH7125_08 Datasheet, PDF (618/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Flash Memory
(2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU)
This parameter indicates the return value of the initialization result.
Bit: 31
-
Initial value: -
R/W: R/W
30
-
-
R/W
29
-
-
R/W
28
-
-
R/W
27
-
-
R/W
26
-
-
R/W
25
-
-
R/W
24
-
-
R/W
23
-
-
R/W
22
-
-
R/W
21
-
-
R/W
20
-
-
R/W
19
-
-
R/W
18
-
-
R/W
17
-
-
R/W
16
-
-
R/W
Bit: 15
-
Initial value: -
R/W: R/W
14
-
-
R/W
13
-
-
R/W
12
-
-
R/W
11
-
-
R/W
10
-
-
R/W
9
-
-
R/W
8
-
-
R/W
7
-
-
R/W
6
-
-
R/W
5
-
-
R/W
4
-
-
R/W
3
-
-
R/W
2
BR
-
R/W
1
FQ
-
R/W
0
SF
-
R/W
Initial
Bit
Bit Name Value
R/W
31 to 3 
Undefined R/W
2
BR
Undefined R/W
1
FQ
Undefined R/W
0
SF
Undefined R/W
Description
Unused
Return 0.
User Branch Error Detect
Returns the check result whether the specified user
branch destination address is in the area other than the
storage area of the programming/erasing program
which has been downloaded.
0: User branch address setting is normal
1: User branch address setting is abnormal
Frequency Error Detect
Returns the check result whether the specified
operating frequency of the CPU is in the range of the
supported operating frequency.
0: Setting of operating frequency is normal
1: Setting of operating frequency is abnormal
Success/Fail
Indicates whether initialization is completed normally.
0: Initialization has ended normally (no error)
1: Initialization has ended abnormally (error occurs)
Rev. 4.00 Jul. 25, 2008 Page 598 of 750
REJ09B0243-0400