SH7125_08 Datasheet, PDF (604/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Flash Memory
Table 17.4 (1) Register Configuration
Register Name
Abbreviation*³ R/W
Initial
Value
Address
Access
Size
Flash code control and status
register
FCCS
R, W*¹ H'00*² H'FFFFCC00 8
H'80*²
Flash program code select register FPCS
R/W H'00 H'FFFFCC01 8
Flash erase code select register FECS
R/W H'00 H'FFFFCC02 8
Flash key code register
FKEY
R/W H'00 H'FFFFCC04 8
Flash transfer destination address FTDAR
register
R/W H'00 H'FFFFCC06 8
Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit.
(The value, which can be read is always 0.)
2. The initial value of the FWE bit is 0 when the FWE pin goes low.
The initial value of the FWE bit is 1 when the FWE pin goes high.
3. All registers can be accessed only in bytes.
Table 17.4 (2) Parameter Configuration
Name
Abbreviation R/W
Initial
Value
Address
Access
Size
Download pass/fail result DPFR
R/W Undefined On-chip RAM* 8, 16, 32
Flash pass/fail result
FPFR
R/W Undefined R0 of CPU 8, 16, 32
Flash multipurpose address FMPAR
area
R/W Undefined R5 of CPU 8, 16, 32
Flash multipurpose data
destination area
FMPDR
R/W Undefined R4 of CPU 8, 16, 32
Flash erase block select
FEBS
R/W Undefined R4 of CPU 8, 16, 32
Flash program and erase
frequency control
FPEFEQ
R/W Undefined R4 of CPU 8, 16, 32
Flash user branch address FUBRA
set parameter
R/W Undefined R5 of CPU 8, 16, 32
Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid.
Rev. 4.00 Jul. 25, 2008 Page 584 of 750
REJ09B0243-0400