SH7125_08 Datasheet, PDF (82/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
15

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12 IFC[2:0] 011
R/W Internal Clock (Iφ) Frequency Division Ratio
Specify the division ratio of the internal clock (Iφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: Setting prohibited
001: ×1/2
010: Setting prohibited
011: ×1/4 (initial value)
100: ×1/8
Other than above: Setting prohibited
11 to 9 BFC[2:0] 011
R/W Bus Clock (Bφ) Frequency Division Ratio
Specify the division ratio of the bus clock (Bφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: Setting prohibited
001: ×1/2
010: Setting prohibited
011: ×1/4 (initial value)
100: ×1/8
Other than above: Setting prohibited
Rev. 4.00 Jul. 25, 2008 Page 62 of 750
REJ09B0243-0400