SH7125_08 Datasheet, PDF (297/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
7. PWM Cycle Setting
In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in
which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit
value is set. The settings should be made so as to achieve the following relationship between
these two registers:
With dead time: TGRA_3 set value = TCDR set value + TDDR set value
Without dead time: TGRA_3 set value = TCDR set value + 1
The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3
and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3
and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer
mode register (TMDR).
The updated PWM cycle is reflected from the next cycle when the data update is performed at
the crest, and from the current cycle when performed in the trough. Figure 9.42 illustrates the
operation when the PWM cycle is updated at the crest.
See the following section, Register Data Updating, for the method of updating the data in each
buffer register.
Counter value
TGRC_3
update
TGRA_3
update
TGRA_3
TCNT_3
TCNT_4
Time
Figure 9.42 Example of PWM Cycle Updating
Rev. 4.00 Jul. 25, 2008 Page 277 of 750
REJ09B0243-0400