SH7125_08 Datasheet, PDF (443/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
Initial
Bit
Bit Name value R/W Description
6
RDRF
0
R/(W)* Receive Data Register Full
Indicates that the received data is stored in the
receive data register (SCRDR).
0: Indicates that valid received data is not stored in
SCRDR
[Clearing conditions]
• By a power-on reset or in standby mode
• When 0 is written to RDRF after reading RDRF =
1
1: Indicates that valid received data is stored in
SCRDR
[Setting condition]
• When serial reception ends normally and receive
data is transferred from SCRSR to SCRDR
Note: SCRDR and the RDRF flag are not affected and
retain their previous states even if an error is
detected during data reception or if the RE bit in
the serial control register (SCSCR) is cleared to
0. If reception of the next data is completed
while the RDRF flag is still set to 1, an overrun
error will occur and the received data will be
lost.
Rev. 4.00 Jul. 25, 2008 Page 423 of 750
REJ09B0243-0400