SH7125_08 Datasheet, PDF (420/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
10.6 Usage Note
10.6.1 Pin State when a Power-On Reset is Issued from the Watchdog Timer
When a power-on reset is issued from the watchdog timer (WDT), initialization of the pin function
controller (PFC) sets initial values that select the general input function for the I/O ports.
However, when a power-on reset is issued from the WDT while a pin is being handled as high
impedance by the port output enable (POE), the pin is placed in the output state for one cycle of
the peripheral clock (Pf), after which the function is switched to general input.
This also occurs when a power-on reset is issued from the WDT for pins that are being handled as
high impedance due to short-circuit detection by the MTU2.
Figure 10.5 shows the state of a pin for which the POE input has selected high impedance
handling with the timer output selected when a power-on reset is issued from the WDT.
Pφ
POE input
Pin state
Timer output
PFC setting value
Timer output
High impedance state
Timer
output
1Pφ cycle
General input
General input
Power-on reset by WDT
Figure 10.5 Pin State when a Power-On Reset is Issued from the Watchdog Timer
Rev. 4.00 Jul. 25, 2008 Page 400 of 750
REJ09B0243-0400