SH7125_08 Datasheet, PDF (62/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
2.5.5 Shift Instructions
Table 2.14 Shift Instructions
Instruction
ROTL Rn
ROTR Rn
ROTCL Rn
ROTCR Rn
SHAL Rn
SHAR Rn
SHLL Rn
SHLR Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Operation
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
T ← Rn ← 0
MSB → Rn → T
T ← Rn ← 0
0 → Rn → T
Rn << 2 → Rn
Rn >> 2 → Rn
Rn << 8 → Rn
Rn >> 8 → Rn
Rn << 16 → Rn
Rn >> 16 → Rn
Code
Execution
Cycles
0100nnnn00000100 1
0100nnnn00000101 1
0100nnnn00100100 1
0100nnnn00100101 1
0100nnnn00100000 1
0100nnnn00100001 1
0100nnnn00000000 1
0100nnnn00000001 1
0100nnnn00001000 1
0100nnnn00001001 1
0100nnnn00011000 1
0100nnnn00011001 1
0100nnnn00101000 1
0100nnnn00101001 1
T Bit
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
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Rev. 4.00 Jul. 25, 2008 Page 42 of 750
REJ09B0243-0400