SH7125_08 Datasheet, PDF (269/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
TCLKC
TCLKD
TCNT_2
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
TCNT_1
0000
0001
0000
Figure 9.21 Cascaded Operation Example (a)
Cascaded Operation Example (b) in SH7125: Figure 9.22 illustrates the operation when
TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include
the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits
in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to
IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing.
Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1
input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used.
TCNT_2 value
H'FFFF
H'C256
H'6128
H'0000
TCNT_1
TIOC1A
TIOC2A
TGRA_1
TGRA_2
H'0512
H'0513
H'0514
Time
H'0512
H'0513
H'C256
As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing.
Figure 9.22 Cascaded Operation Example (b)
Rev. 4.00 Jul. 25, 2008 Page 249 of 750
REJ09B0243-0400