SH7125_08 Datasheet, PDF (13/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

9.3.13 Timer General Register (TGR) ............................................................................. 209
9.3.14 Timer Start Register (TSTR) ................................................................................ 210
9.3.15 Timer Synchronous Register (TSYR)................................................................... 212
9.3.16 Timer Read/Write Enable Register (TRWER) ..................................................... 214
9.3.17 Timer Output Master Enable Register (TOER) .................................................... 215
9.3.18 Timer Output Control Register 1 (TOCR1).......................................................... 216
9.3.19 Timer Output Control Register 2 (TOCR2).......................................................... 219
9.3.20 Timer Output Level Buffer Register (TOLBR) .................................................... 222
9.3.21 Timer Gate Control Register (TGCR) .................................................................. 223
9.3.22 Timer Subcounter (TCNTS) ................................................................................. 225
9.3.23 Timer Dead Time Data Register (TDDR)............................................................. 226
9.3.24 Timer Cycle Data Register (TCDR) ..................................................................... 226
9.3.25 Timer Cycle Buffer Register (TCBR)................................................................... 227
9.3.26 Timer Interrupt Skipping Set Register (TITCR)................................................... 227
9.3.27 Timer Interrupt Skipping Counter (TITCNT)....................................................... 229
9.3.28 Timer Buffer Transfer Set Register (TBTER) ...................................................... 230
9.3.29 Timer Dead Time Enable Register (TDER) ......................................................... 232
9.3.30 Timer Waveform Control Register (TWCR) ........................................................ 233
9.3.31 Bus Master Interface............................................................................................. 234
9.4 Operation ........................................................................................................................... 235
9.4.1 Basic Functions..................................................................................................... 235
9.4.2 Synchronous Operation......................................................................................... 241
9.4.3 Buffer Operation................................................................................................... 243
9.4.4 Cascaded Operation .............................................................................................. 247
9.4.5 PWM Modes......................................................................................................... 252
9.4.6 Phase Counting Mode........................................................................................... 257
9.4.7 Reset-Synchronized PWM Mode ......................................................................... 264
9.4.8 Complementary PWM Mode................................................................................ 267
9.4.9 A/D Converter Start Request Delaying Function.................................................. 308
9.4.10 External Pulse Width Measurement...................................................................... 312
9.4.11 Dead Time Compensation .................................................................................... 313
9.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 315
9.5 Interrupt Sources................................................................................................................ 316
9.5.1 Interrupt Sources and Priorities ............................................................................ 316
9.5.2 A/D Converter Activation..................................................................................... 319
9.6 Operation Timing............................................................................................................... 321
9.6.1 Input/Output Timing ............................................................................................. 321
9.6.2 Interrupt Signal Timing ........................................................................................ 328
9.7 Usage Notes ....................................................................................................................... 332
9.7.1 Module Standby Mode Setting ............................................................................. 332
Rev. 4.00 Jul. 25, 2008 Page xiii of xx