SH7125_08 Datasheet, PDF (32/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
Classification
System control
Symbol
I/O
RES
I
MRES
I
WDTOVF O
Interrupts
NMI
I
IRQ3 to IRQ0 I
(SH7125)
IRQ3 to IRQ1
(SH7124)
IRQOUT
O
Multi function timer- TCLKA,
I
pulse unit 2 (MTU2) TCLKB,
TCLKC,
TCLKD
TIOC0A,
I/O
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
I/O
TIOC1B
(only in
SH7125)
TIOC2A,
I/O
TIOC2B
(only in
SH7125)
Name
Function
Power-on reset When low, this LSI enters the power-
on reset state.
Manual reset
When low, this LSI enters the
manual reset state.
Watchdog timer Output signal for the watchdog timer
overflow
overflow
If this pin needs to be pulled down,
use the resistor larger than
1 MΩ to pull this pin down.
Non-maskable
interrupt
Non-maskable interrupt request pin
Fix to high or low level when not in
use.
Interrupt requests Maskable interrupt request pins
3 to 0
Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
Interrupt request
output
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release
state.
MTU2 timer clock External clock input pins for the timer
input
MTU2 input
capture/output
compare
(channel 0)
MTU2 input
capture/output
compare
(channel 1)
MTU2 input
capture/output
compare
(channel 2)
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins
The TGRA_1 to TGRB_1 input
capture input/output compare
output/PWM output pins
The TGRA_2 to TGRB_2 input
capture input/output compare
output/PWM output pins
Rev. 4.00 Jul. 25, 2008 Page 12 of 750
REJ09B0243-0400