SH7125_08 Datasheet, PDF (355/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.7.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the
compare match signal is also generated.
Figure 9.110 shows the timing in this case.
MPφ
Address
TGR write cycle
T1 T2
TGR address
Write signal
Compare
match signal
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 9.110 Contention between TGR Write and Compare Match
Rev. 4.00 Jul. 25, 2008 Page 335 of 750
REJ09B0243-0400