SH7125_08 Datasheet, PDF (760/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
4.4.2 Oscillation Stop Detection
Control Register (OSCCR)
Page Revision (See Manual for Details)
64 Deleted
Initial
Bit Bit Name Value R/W Description
2 OSCSTOP 0
R Oscillation Stop Detection Flag
[Setting conditions]
• When a stop in the clock
input is detected during
normal operation
• When software standby
mode is entered
[Clearing conditions]
• By a power-on reset input
through the RES pin
• When software standby
mode is canceled
4.5 Changing Frequency
65 Deleted
4. After an instruction to rewrite FRQCR has been
issued, the actual clock frequencies will change after
(1 to 24n) cyc + 11Bφ + 7Pφ.
n: Division ratio specified by the BFC bit in FRQCR
(1, 1/2, 1/4, or 1/8)
cyc: Clock obtained by dividing EXTAL by 8 with the
PLL.
Rev. 4.00 Jul. 25, 2008 Page 740 of 750
REJ09B0243-0400