SH7125_08 Datasheet, PDF (741/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 21 Electrical Characteristics
21.3.6 Serial Communication Interface (SCI) Timing
Table 21.10 Serial Communication Interface (SCI) Timing
Conditions: V_CC = AV_CC = 4.0 V to 5.5 V, V_SS = PLLV_SS = AV_SS = 0 V,
T_a = –20 to +85°C (consumer specifications),
T_a = –40 to +85°C (industrial specifications)
Item
Symbol Min.
Max.
Input clock cycle (asynchronous)
t_scyc
Input clock cycle (clock synchronous)
t_scyc
Input clock pulse width
t_sckw
Input clock rising time
t_sckr
Input clock falling time
t_sckf
Transmit data delay time
Asynchronous t_TXD
Receive data setup time
t_RXS
Receive data hold time
t_RXH
Transmit data delay time
Receive data setup time
Clock
t_TXD
synchronous
t_RXS
Receive data hold time
t_RXH
Note:
t
pcyc
indicates
the
peripheral
clock
(Pφ)
cycle.
4

6

0.4
0.6

1.5

1.5

4 t_pcyc + 10
4 t_pcyc

4 t_pcyc


3 t_pcyc + 10
2 t_pcyc + 50 
2 t_pcyc

Unit
t_pcyc
t_pcyc
t_scyc
t_pcyc
t_pcyc
ns
ns
ns
ns
ns
ns
Reference
Figure
Figure
21.12
Figure
21.13
SCK0 to SCK2
t_sckw
V_IH
V_IH
V_IL
t_sckr
V_IH
V_IL
t_scyc
Figure 21.12 Input Clock Timing
t_sckf
V_IH
V_IL
Rev. 4.00 Jul. 25, 2008 Page 721 of 750
REJ09B0243-0400