SH7125_08 Datasheet, PDF (403/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
10.2 Input/Output Pins
Table 10.1 Pin Configuration
Name
Abbreviation
I/O
Description
Port output enable input pins POE0, POE1,
0, 1, 3
POE3*
Input
Input request signals to place high-
current pins for MTU2 in high-
impedance state*
Port output enable input pin 8 POE8
Input
Inputs a request signal to place pins
for channel 0 in MTU2 in high-
impedance state*
Note: * When the POE3 function is selected in the PFC, the pin is pulled up inside the LSI if
nothing is input to it. The POE3 pin is supported only by the SH7125.
Table 10.2 shows output-level comparisons with pin combinations.
Table 10.2 Pin Combinations
Pin Combination
PE9/TIOC3B and PE11/TIOC3D
PE12/TIOC4A and PE14/TIOC4C
PE13/TIOC4B and PE15/TIOC4D
I/O
Description
Output
The high-current pins for the MTU2 are placed in
high-impedance state when the pins
simultaneously output an active level (low level
when the output level select P (OLSP) bit of the
timer output control register (TOCR) in the MTU2 is
0 or high level when the bit is 1) for one or more
cycles of the peripheral clock (Pφ).
This active level comparison is done when the
MTU2 output function or general output function is
selected in the pin function controller. If another
function is selected, the output level is not
checked.
Pin combinations for output comparison and high-
impedance control can be selected by POE
registers.
Rev. 4.00 Jul. 25, 2008 Page 383 of 750
REJ09B0243-0400