SH7125_08 Datasheet, PDF (321/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Interrupt skipping
Clear interrupt skipping counter [1]
Set skipping count and
enable interrupt skipping
[2]
<Interrupt skipping>
[1] Set bits T3AEN and T4VEN in the timer interrupt
skipping set register (TITCR) to 0 to clear the
skipping counter.
[2] Specify the interrupt skipping count within the
range from 0 to 7 times in bits 3ACOR2 to
3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and
enable interrupt skipping through bits T3AEN and
T4VEN.
Note: The setting of TITCR must be done while the
TGIA_3 and TCIV_4 interrupt requests are
disabled by the settings of registers TIER_3
and TIER_4 along with under the conditions in
which TGFA_3 and TCFV_4 flag settings by
compare match never occur.
Before changing the skipping count, be sure to
clear the T3AEN and T4VEN bits to 0 to clear
the skipping counter.
Figure 9.67 Example of Interrupt Skipping Operation Setting Procedure
TCNT_3
TCNT_4
Period during which
changing skipping count
can be performed
Period during which
changing skipping count
can be performed
Period during which
changing skipping count
can be performed
Period during which
changing skipping count
can be performed
Figure 9.68 Periods during which Interrupt Skipping Count can be Changed
2. Example of Interrupt Skipping Operation
Figure 9.69 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping
count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt
skipping set register (TITCR).
Rev. 4.00 Jul. 25, 2008 Page 301 of 750
REJ09B0243-0400