HD6473032F16 Datasheet, PDF (94/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 3 MCU Operating Modes
3.4.6 Mode 6
Ports 1, 2, and 5 and part of port A function as address pins A₂₃ to A₀, permitting access to a
maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,
and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,
and P5DDR) must be set to 1. For A₂₃ to A₂₁ output, clear bits 7 to 5 of BRCR to 0. (In this mode
A₂₀ is always used for address output.)
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.7 Mode 7
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 7 supports a 1-Mbyte address space.
3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3
indicates their functions in each operating mode.
Table 3.3 Pin Functions in Each Mode
Port
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Port 1
Port 2
A7 to A0
A15 to A8
A7 to A0
A15 to A8
A7 to A0
A15 to A8
A7 to A0
A15 to A8
P17 to P10^*2
P27 to P20^*2
P17 to P10^*2
P27 to P20^*2
P17 to P10
P27 to P20
Port 3 D15 to D8
D15 to D8
D15 to D8
D15 to D8
D15 to D8
D15 to D8
P37 to P30
Port 4 P47 to P40^*1 D7 to D0^*1
P47 to P40^*1 D7 to D0^*1
P47 to P40^*1 P47 to P40^*1 P47 to P40
Port 5 A19 to A16
A19 to A16
A19 to A16
A19 to A16
P53 to P50^*2 P53 to P50^*2 P53 to P50
Port A
PA7 to PA4
PA7 to PA4
PA7 to PA5^*3, PA7 to PA5^*3, PA7 to PA4
A20
A20
PA7 to PA5,
A20^*3
PA7 to PA4
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.
2. Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
3. Initial state. A20 is always an address output pin. PA7 to PA5 are switched over to A23 to
A21 output by writing 0 in bits 7 to 5 of BRCR.
Rev. 3.00 Mar 21, 2006 page 64 of 814
REJ09B0302-0300