HD6473032F16 Datasheet, PDF (36/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 1 Overview
1.2 Block Diagram
Figure 1.1 shows an internal block diagram.
MD2
MD1
MD0
EXTAL
XTAL
φ
STBY
RES
FWE
NMI
P66/LWR
P65/HWR
P64/RD
P63/AS
P62/BACK
P61/BREQ
P60/WAIT
P84/CS0
P83/CS1/IRQ3
P82/CS2/IRQ2
P81/CS3/IRQ1
P80/RFSH/IRQ0
Port 3
Address bus
Data bus (upper)
Data bus (lower)
Port 4
H8/300H CPU
Interrupt controller
ROM
(flash memory)
RAM
16-bit integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
DMA controller
(DMAC)
Refresh
controller
Watchdog timer
(WDT)
Serial communication
interface
(SCI) × 2 channels
A/D converter
D/A converter
P53/A19
P52/A18
P51/A17
P50/A16
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RxD1
P92/RxD0
P91/TxD1
P90/TxD0
Port B
Port A
Port 7
Figure 1.1 Block Diagram
Rev. 3.00 Mar 21, 2006 page 6 of 814
REJ09B0302-0300