HD6473032F16 Datasheet, PDF (371/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with
non-overlapping complementary waveforms. When complementary PWM mode is selected
GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and
TIOCA₃, TIOCB₃, TIOCA₄, TOCXA₄, TIOCB₄, and TOCXB₄ function as PWM output pins.
TCNT3 and TCNT4 operate as up/down-counters.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/down-
counter.
Buffering
• If the general register is an output compare register
When compare match occurs the buffer register value is transferred to the general register.
• If the general register is an input capture register
When input capture occurs the TCNT value is transferred to the general register, and the
previous general register value is transferred to the buffer register.
• Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction.
• Reset-synchronized PWM mode
The buffer register value is transferred to the general register at GRA3 compare match.
10.4.2 Basic Functions
Counter Operation: When one of bits STR0 to STR4 is set to 1 in the timer start register (TSTR),
the timer counter (TCNT) in the corresponding channel starts counting. The counting can be free-
running or periodic.
• Sample setup procedure for counter
Figure 10.14 shows a sample procedure for setting up a counter.
Rev. 3.00 Mar 21, 2006 page 341 of 814
REJ09B0302-0300