HD6473032F16 Datasheet, PDF (129/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 5 Interrupt Controller
1. If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. When the interrupt controller receives one or more interrupt requests, it selects the highest-
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
3. The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held
pending.
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
5. In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
6. Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
7. The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of IRQ₀
to IRQ₅ interrupts and interrupts from the on-chip supporting modules.
• Interrupt requests with priority level 0 are enabled when the I bit is cleared to 0, and disabled
when the I bit is set to 1.
• Interrupt requests with priority level 1 are enabled when the I bit or UI bit is cleared to 0, and
disabled when the I bit and UI bit are both set to 1.
For example, if the interrupt enable bits of all interrupt requests are set to 1, and IPRA and
IPRB are set to H'20 and H'00, respectively (giving IRQ₂ and IRQ₃ interrupt requests priority
over other interrupts), interrupts are enabled and disabled as follows:
a. If I = 0, all interrupts are enabled (priority order: NMI > IRQ₂ > IRQ₃ > IRQ₀ ...).
b. If I = 1 and UI = 0, only NMI, IRQ₂, and IRQ₃ are enabled.
c. If I = 1 and UI = 1, all interrupts are disabled except NMI.
Figure 5.5 shows the transitions among the above states.
Rev. 3.00 Mar 21, 2006 page 99 of 814
REJ09B0302-0300