HD6473032F16 Datasheet, PDF (19/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 5 Interrupt Controller .......................................................................................... 79
5.1 Overview........................................................................................................................... 79
5.1.1 Features................................................................................................................ 79
5.1.2 Block Diagram ..................................................................................................... 80
5.1.3 Pin Configuration................................................................................................. 81
5.1.4 Register Configuration......................................................................................... 81
5.2 Register Descriptions ........................................................................................................ 82
5.2.1 System Control Register (SYSCR) ...................................................................... 82
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 83
5.2.3 IRQ Status Register (ISR).................................................................................... 89
5.2.4 IRQ Enable Register (IER) .................................................................................. 90
5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 91
5.3 Interrupt Sources ............................................................................................................... 92
5.3.1 External Interrupts ............................................................................................... 92
5.3.2 Internal Interrupts................................................................................................. 93
5.3.3 Interrupt Exception Vector Table ........................................................................ 93
5.4 Interrupt Operation............................................................................................................ 97
5.4.1 Interrupt Handling Process................................................................................... 97
5.4.2 Interrupt Exception Handling Sequence .............................................................. 102
5.4.3 Interrupt Response Time...................................................................................... 103
5.5 Usage Notes ...................................................................................................................... 104
5.5.1 Contention between Interrupt Generation and Disabling..................................... 104
5.5.2 Instructions that Inhibit Interrupts........................................................................ 105
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 105
5.5.4 Notes on Use of External Interrupts..................................................................... 105
Section 6 Bus Controller.................................................................................................... 109
6.1 Overview........................................................................................................................... 109
6.1.1 Features................................................................................................................ 109
6.1.2 Block Diagram ..................................................................................................... 110
6.1.3 Pin Configuration................................................................................................. 111
6.1.4 Register Configuration......................................................................................... 112
6.2 Register Descriptions ........................................................................................................ 112
6.2.1 Bus Width Control Register (ABWCR)............................................................... 112
6.2.2 Access State Control Register (ASTCR) ............................................................. 113
6.2.3 Wait Control Register (WCR).............................................................................. 114
6.2.4 Wait State Controller Enable Register (WCER) .................................................. 115
6.2.5 Bus Release Control Register (BRCR) ................................................................ 116
6.2.6 Chip Select Control Register (CSCR).................................................................. 118
Rev. 3.00 Mar 21, 2006 page xvii of xxviii