HD6473032F16 Datasheet, PDF (544/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 14 Smart Card Interface
This procedure may include interrupt handling and DMA transfer.
If the RIE bit is set to 1 to enable interrupt requests, when receiving is completed and the RDRF
flag is set to 1, a receive-data-full interrupt (RXI) is requested. If a receive error occurs, either the
ORER or PER flag is set to 1 and a transmit/receive-error interrupt (ERI) is requested.
If the RXI interrupt activates the DMAC, the number of bytes designated in the DMAC will be
transferred, skipping receive data in which an error occurred.
For details, see Interrupt Operations and Data Transfer by DMAC below.
When a parity error occurs and PER is set to 1, the receive data is transferred to RDR, so the
erroneous data can be read.
Switching Modes: To switch from receive mode to transmit mode, check that receiving
operations have completed, then initialize the smart card interface, clearing RE to 0 and setting TE
to 1. Completion of receive operations is indicated by the RDRF, PER, or ORER flag.
To switch from transmit mode to receive mode, check that transmitting operations have
completed, then initialize the smart card interface, clearing TE to 0 and setting RE to 1.
Completion of transmit operations can be verified from the TEND flag.
Fixing Clock Output: When the GM bit of the SMR is set to 1, clock output is fixed by CKE1
and CKE0 of SCR. In this case, the clock pulse can be set at minimum value.
Figure 14.8 shows clock output fixed timing: CKE0 is restricted with GM = 1 and CKE1 = 1.
SCK
Specified pulse width
CKE1 value
Specified pulse width
SCR write
(CKE0 = 0)
SCR write
(CKE0 = 1)
Figure 14.8 Clock Output Fixed Timing
Rev. 3.00 Mar 21, 2006 page 514 of 814
REJ09B0302-0300