HD6473032F16 Datasheet, PDF (191/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Read cycle
Write cycle*
Section 7 Refresh Controller
Refresh cycle
φ
Address
bus
CS 3
(RAS)
HWR
(UCAS)
HWR
(UW)
LWR
(LW)
RFSH
Row
Column
Row
Column
Area 3 top address
AS
Note: * 16-bit access
Figure 7.5 DRAM Control Signal Output Timing (2) (2CAS Mode)
Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is:
(High) External bus master > refresh controller > DMA controller > CPU (Low)
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion: When bit AST3 is set to 1 in ASTCR, bus controller settings can cause wait
states to be inserted into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
Rev. 3.00 Mar 21, 2006 page 161 of 814
REJ09B0302-0300