HD6473032F16 Datasheet, PDF (250/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
8.4.6 Block Transfer Mode
In block transfer mode the A and B channels are combined. One block of a specified size is
transferred per request. A designated number of block transfers are executed. Addresses are
specified in MARA and MARB. The block area address can be either held fixed or cycled.
Table 8.10 indicates the register functions in block transfer mode.
Table 8.10 Register Functions in Block Transfer Mode
Register
23
0
MARA
23
0
MARB
7
0
ETCRAH
7
0
ETCRAL
Function
Source address
register
Destination
address register
Block size
counter
Initial block size
Initial Setting
Source address
Destination
address
Block size
Block size
Operation
Incremented or
decremented once per
transfer, or held fixed
Incremented or
decremented once per
transfer, or held fixed
Decremented once per
transfer until H'00 is
reached, then reloaded
from ETCRAL
Held fixed
Block transfer
15
0 _counter
ETCRB
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
ETCRB: Execute transfer count register B
Number of block
transfers
Decremented once per
block transfer until H'0000
is reached and the
transfer ends
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred. One of these registers operates as a
block area register: even if it is incremented or decremented, it is restored to its initial value at the
end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or
destination.
Rev. 3.00 Mar 21, 2006 page 220 of 814
REJ09B0302-0300