HD6473032F16 Datasheet, PDF (262/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
Figure 8.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
φ
DREQ
End of 1 block transfer
DMAC cycle
CPU cycle
DMAC cycle
T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
Address
bus
RD
HWR , LWR
TEND
Next sampling
Minimum 4 states
Figure 8.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode
Rev. 3.00 Mar 21, 2006 page 232 of 814
REJ09B0302-0300