HD6473032F16 Datasheet, PDF (14/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Item
Page
21.2.2 AC Characteristics 639
Table 21.7 Timing of On-
Chip Supporting Modules
21.2.3 A/D Conversion 640
Characteristics
Table 21.8 A/D Converter
Characteristics
21.2.4 D/A Conversion 641
Characteristics
Table 21.9 D/A Converter
Characteristics
21.2.5 Flash Memory
Characteristics
642, 643
Table 21.10 Flash
Memory Characteristics
A.1 Instruction List
663
Table A.1 Instruction Set
2. Arithmetic instructions
Revisions (See Manual for Details)
Condition A and Condition B deleted
Table and notes amended
Item
DMAC
ITU
DREQ setup time
DREQ hold time
TEND delay time 1
TEND delay time 2
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Single edge
Both edges
Symbol
tDRQS
tDRQH
tTED1
tTED2
tTOCD
tTICS
tTCKS
tTCKWH
tTCKWL
Conditions
Min
Max
20
—
10
—
—
50
—
50
—
50
40
—
40
—
1.5
—
2.5
—
Unit
ns
ns
tcyc
tscyc
Test
Conditions
Figure 21.16
Figure 21.24,
Figure 21.25
Figure 21.20
Figure 21.21
Condition A and Condition B deleted
Table and notes amended
Item
Min
Conversion time
5.36
Notes: 1 The value is for φ ≤ 13 MHz.
2 The value is for φ > 13 MHz.
Condition A and Condition B deleted
Conditions
Typ
Max
—
—
Condition A and Condition B deleted
Table and notes amended
Conditions
Item
Symbol Min Typ
Max Unit
Notes
Reprogramming count
Data retention period
NWEC
TDRP
100^*6 10.000^*7 —
10^*8 —
—
Times
Years
Notes: 6. Minimum cycle value which guarantees all characteristics after reprogramming.
(Reprogram cycles from 1 to minimum value are guaranteed.)
7. Reference characteristics at 25˚C. (This is a indication that reprogram operation can
normally function up to this figure.)
8. Data retention characteristics when reprogaram performed correctly within
specification value including minimum data retention period.
Table amended
Addressing Mode and
Instruction Length (bytes)
No. of
States^*1
Mnemonic
Operation
Condition Code
DAA Rd
B Rd8 decimal adjust
2
→ Rd8
I HNZVC
—
*
2
Rev. 3.00 Mar 21, 2006 page xii of xxviii