HD6473032F16 Datasheet, PDF (56/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 2 CPU
carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or
NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and
cleared to 0 otherwise.
• Bit 4—User Bit (U)
Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC
instructions.
• Bit 3—Negative Flag (N)
Indicates the most significant bit (sign bit) of data.
• Bit 2—Zero Flag (Z)
Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
• Bit 1—Overflow Flag (V)
Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
• Bit 0—Carry Flag (C)
Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
 Add instructions, to indicate a carry
 Subtract instructions, to indicate a borrow
 Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. The initial
value of the stack pointer (ER7) is undefined. The stack pointer must therefore be initialized by an
MOV.L instruction executed immediately after a reset.
Rev. 3.00 Mar 21, 2006 page 26 of 814
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