HD6473032F16 Datasheet, PDF (420/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between Buffer Register Write and Input Capture: If a buffer register is used for
input capture buffering and an input capture signal occurs in the T₃ state of a write cycle, input
capture takes priority and the write to the buffer register is not performed. See figure 10.69.
Buffer register write cycle
T₁
T₂
T₃
φ
Address bus
BR address
Internal write signal
Input capture signal
GR
N
X
TCNT value
BR
M
N
Figure 10.69 Contention between Buffer Register Write and Input Capture
Rev. 3.00 Mar 21, 2006 page 390 of 814
REJ09B0302-0300