HD6473032F16 Datasheet, PDF (416/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T₃
state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set
to 1.The same holds for underflow. See figure 10.65.
TCNT write cycle
T₁
T₂
T₃
φ
Address bus
TCNT address
Internal write signal
TCNT input clock
Overflow signal
TCNT
OVF
H'FFFF
M
TCNT write data
Figure 10.65 Contention between TCNT Write and Overflow
Rev. 3.00 Mar 21, 2006 page 386 of 814
REJ09B0302-0300