HD6473032F16 Datasheet, PDF (673/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 21 Electrical Characteristics
Notes: 1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes. (Shows the total time the P1 bit or P2 bit in the flash
memory control register (FLMCR1 or FLMCR2) is set. It does not include the
programming verification time.)
3. Block erase time. (Shows the total time the E1 bit in FLMCR1 or E2 bit in FLMCR2 is
set. It does not include the erase verification time.)
4. To specify the maximum programming time value (tP(max)) in the 128-byte
programming algorithm, set the max. value (1000) for the maximum programming count
(N).
The wait time after P bit setting should be changed as follows according to the value of
the programming counter (n).
Programming counter (n) = 1 to 6:
tsp30 = 30 µs
Programming counter (n) = 7 to 1000:
tsp200 = 200 µs
Programming counter (n) [in additional programming] = 1 to 6: tsp10 = 10 µs
5. For the maximum erase time (tE(max)), the following relationship applies between the
wait time after E bit setting (tse) and the maximum erase count (N):
tE(max) = Wait time after E bit setting (tse) × maximum erase count (N)
To set the maximum erase time, the values of tse and N should be set so as to satisfy
the above formula.
Examples: When tse = 100 [ms], N = 12
When tse = 10 [ms], N = 120
6. Minimum cycle value which guarantees all characteristics after reprogramming.
(Reprogram cycles from 1 to minimum value are guaranteed.)
7. Reference characteristics at 25°C. (This is a indication that reprogram operation can
normally function up to this figure.)
8. Data retention characteristics when reprogaram performed correctly within
specification value including minimum data retention period.
21.3 Operational Timing
This section shows timing diagrams.
21.3.1 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 21.4 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 21.5 shows the timing of the external three-state access cycle.
Rev. 3.00 Mar 21, 2006 page 643 of 814
REJ09B0302-0300