HD6473032F16 Datasheet, PDF (601/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 18 ROM
18.5.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the
SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be
erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can
be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be
automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
The flash memory block configuration is shown in table 18.3.
Bit
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
18.5.4 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin. Bits EB11 to EB8 will be initialized to 0 if bit SWE1 of
FLMCR1 is not set, even though a high level is input to pin FWE. Also, bits EB15 to EB12 will be
initialized to 0 if bit SWE2 of FLMCR2 is not set. When a bit in EBR2 is set to 1, the
corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1
and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both
EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read
will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 18.3.
Bit
7
6
5
4
3
2
1
0
EB15 EB14 EB13 EB12 EB11 EB10
EB9
EB8
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.00 Mar 21, 2006 page 571 of 814
REJ09B0302-0300