HD6473032F16 Datasheet, PDF (228/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
8.3 Register Descriptions (Full Address Mode)
In full address mode the A and B channels operate together. Full address mode is selected as
indicated in table 8.4.
8.3.1 Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the
source address register of the transfer, and MARB as the destination address register.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved: they cannot be modified and always return an undetermined value when
read.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value
Read/Write
Undetermined
Undetermined
— — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W
MARR
MARE
Source or destination address
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value
Undetermined
Undetermined
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MARH
MARL
Source or destination address
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 8.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
Rev. 3.00 Mar 21, 2006 page 198 of 814
REJ09B0302-0300