HD6473032F16 Datasheet, PDF (417/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T₃ state of a general register read cycle, the value before input capture is read.
See figure 10.66.
General register read cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 10.66 Contention between General Register Read and Input Capture
Rev. 3.00 Mar 21, 2006 page 387 of 814
REJ09B0302-0300