HD6473032F16 Datasheet, PDF (457/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 12 Watchdog Timer
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6: WT/IT
0
1
Description
Interval timer: requests interval timer interrupts
Watchdog timer: generates a reset signal
(Initial value)
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
When WT/IT = 1, clear the SYSCR software standby bit (SSBY) to 0, then set the TME to 1.
When SSBY is set to 1, clear TME to 0.
Bit 5: TME
0
1
Description
TCNT is initialized to H'00 and halted
TCNT is counting and CPU interrupt requests are enabled
(Initial value)
Bits 4 and 3—Reserved: Read-only bits, always read as 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources,
obtained by prescaling the system clock (φ), for input to TCNT.
Bit 2: CKS2
0
1
Bit 1: CKS1
0
1
0
1
Bit 0: CKS0
0
1
0
1
0
1
0
1
Description
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
(Initial value)
Rev. 3.00 Mar 21, 2006 page 427 of 814
REJ09B0302-0300