HD6473032F16 Datasheet, PDF (136/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 5 Interrupt Controller
Occurrence Conditions
1. If an ISR register read is executed to clear the IRQaF flag while IRQaF = 1, and then the
IRQbF flag is cleared by the initiation of interrupt exception handling.
2. If there is contention between IRQaF flag clearing and IRQbF generation (IRQaF flag setting)
(when IRQbF = 0 at the time of the ISR read to clear the IRQaF flag, but IRQbF is set to 1
before the write to ISR).
If above setting conditions 1 to 3 and occurrence conditions 1 and 2 are all fulfilled, IRQbF will be
cleared erroneously when the ISR write in occurrence condition 2 is executed, and so interrupt
exception handling will not be carried out.
However, the IRQbF flag will not be cleared erroneously if 0 is written to it at least once between
occurrence conditions 1 and 2.
IRQaF
IRQbF
Read Write
10
Read Write
1
0
Read Write IRQb
11
Execution
Occurrence condition 1
Read Write
0
0
Clear in error
Occurrence condition 2
Figure 5.9 IRQnF Flag when Interrupt Processing Is Not Conducted
Either of the following methods can be used to prevent this problem.
• Solution 1
When IRQaF flag clears, do not use the bit computation command, read the ISR in bytes.
When IRQaF only is 0 write all other bits as 1 in bytes.
For example, if a = 0
Rev. 3.00 Mar 21, 2006 page 106 of 814
REJ09B0302-0300