HD6473032F16 Datasheet, PDF (87/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 2 CPU
φ
Address bus
T₁
T₂
Address
AS, RD, HWR, LWR
D₁₅ to D₀
High
High impedance
Figure 2.15 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2.16 shows the on-chip supporting module access
timing. Figure 2.17 indicates the pin states.
φ
Address bus
Read
access
Internal read signal
Internal data bus
Write
access
Internal write signal
Internal data bus
T₁ state
Bus cycle
T₂ state
T₃ state
Address
Read data
Write data
Figure 2.16 Access Cycle for On-Chip Supporting Modules
Rev. 3.00 Mar 21, 2006 page 57 of 814
REJ09B0302-0300