HD6473032F16 Datasheet, PDF(194/847 Page) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD6473032F16 Datasheet, PDF (194/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

◁

Section 7 Refresh Controller

Operation in Power-Down State: The refresh controller operates in sleep mode. It does not

operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR,

RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby

mode.

Example 1: Connection to 2WE 1-Mbit DRAM (1-Mbyte Mode): Figure 7.7 shows typical

interconnections to a 2WE 1-Mbit DRAM, and the corresponding address map. Figure 7.8 shows a

setup procedure to be followed by a program for this example. After power-up the DRAM must be

refreshed to initialize its internal state. Initialization takes a certain length of time, which can be

measured by using an interrupt from another timer module, or by counting the number of times

RTMCSR bit 7 (CMF) is set. Note that no refresh cycle is executed for the first refresh request

after exit from the reset state or standby mode (the first time the CMF flag is set; see figure 7.3).

When using this example, check the DRAM device characteristics carefully and use a procedure

that fits them.

H8/3052BF

A8

A7

A6

A5

A4

A3

A2

A1

2 WE 1-Mbit DRAM with

Ã 16-bit organization

A7

A6

A5

A4

A3

A2

A1

A0

CS 3

RD

HWR

LWR

D15 to D 0

RAS

CAS

UW

LW

OE

I/O15 to I/O 0

a. Interconnections (example)

H'60000

H'7FFFF

DRAM area

Area 3 (1-Mbyte mode)

b. Address map

Figure 7.7 Interconnections and Address Map for 2WE 1-Mbit DRAM (Example)

Rev. 3.00 Mar 21, 2006 page 164 of 814

REJ09B0302-0300

▷