HD6473032F16 Datasheet, PDF (207/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 7 Refresh Controller
Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T₃ state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
performed. See figure 7.20.
RTCNT write cycle by CPU
T₁
T₂
T₃
φ
Address bus
RTCNT address
Internal
write signal
Counter
clear signal
RTCNT
N
H'00
Figure 7.20 Contention between RTCNT Write and Clear
Rev. 3.00 Mar 21, 2006 page 177 of 814
REJ09B0302-0300