HD6473032F16 Datasheet, PDF (264/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
DMAC cycle
(channel 1)
CPU
cycle
DMAC cycle
(channel 0A)
CPU
cycle
DMAC cycle
(channel 1)
T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂
φ
Address
bus
RD
HWR ,
LWR
Figure 8.19 Timing of Multiple-Channel Operations
8.4.10 External Bus Requests, Refresh Controller, and DMAC
During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the refresh controller, the DMAC releases the bus after completing the transfer of the current
byte or word. If there is a transfer request at this point, the DMAC requests the bus right again.
Figure 8.20 shows an example of the timing of insertion of a refresh cycle during a burst transfer
on channel 0.
φ
Address
bus
RD
DMAC cycle (channel 0)
Refresh
cycle
DMAC cycle (channel 0)
T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂
HWR, LWR
Figure 8.20 Bus Timing of Refresh Controller and DMAC
Rev. 3.00 Mar 21, 2006 page 234 of 814
REJ09B0302-0300