HD6473032F16 Datasheet, PDF (620/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 18 ROM
If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and
repeat the erase/erase-verify sequence as before.
Start
*1
Set SWE1 (2) bit in FLMCR1 (2)
Wait tsswe µs
Perform erasing in block units.
*4
n=1
Set EBR1 or EBR2
*3
Enable WDT
Set ESU1 (2) bit in FLMCR1 (2)
Wait tsesu µs
Set E1 (2) bit in FLMCR1 (2)
Wait tse ms
*4
Start of erase
*4
Clear E1 (2) bit in FLMCR1 (2)
Wait tce µs
Clear ESU1 (2) bit in FLMCR1 (2)
Wait tcesu µs
Disable WDT
Set EV1 (2) bit in FLMCR1 (2)
Wait tsev µs
Erase halted
*4
*4
*4
Set block start address as verify address
n←n+1
H'FF dummy write to verify address
Wait tsevr µs
*4
Increment
address
No
Read verify data
*2
No
Verify data = all 1s?
Yes
Last address of block?
Yes
Clear EV1 (2) bit in FLMCR1 (2)
Wait tcev µs
*4
Clear SWE1 (2) bit in FLMCR1 (2)
Wait tcswe µs
*4
End of erasing
Clear EV1 (2) bit in FLMCR1 (2)
Wait tcev µs
*4
*4
No
n ≥ N?
Yes
Clear SWE1 (2) bit in FLMCR1 (2)
Wait tcswe µs
*4
Erase failure
Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Verify data is read in 16-bit (W) units.
3. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.
4. The wait times and the value of N are shown in section 21.2.5, Flash Memory Characteristics.
Figure 18.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
Rev. 3.00 Mar 21, 2006 page 590 of 814
REJ09B0302-0300