HD6473032F16 Datasheet, PDF (234/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit
enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is
enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the
CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further
information on operation in block transfer mode, see section 8.6.6, NMI Interrupts and Block
Transfer Mode.
DTME is set to 1 by reading the register while DTME = 0, then writing 1.
Bit 7: DTME
0
1
Description
Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt occurs)
(Initial value)
Data transfer is enabled
Bit 6—Reserved: Although reserved, this bit can be written and read.
Bit 5—Destination Address Increment/Decrement (DAID) and Bit 4—Destination Address
Increment/Decrement Enable (DAIDE): These bits select whether the destination address
register (MARB) is incremented, decremented, or held fixed during the data transfer.
Bit 5: DAID
0
1
Bit 4: DAIDE Description
0
MARB is held fixed
(Initial value)
1
MARB is incremented after each data transfer
• If DTSZ = 0, MARB is incremented by 1 after each data transfer
• If DTSZ = 1, MARB is incremented by 2 after each data transfer
0
MARB is held fixed
1
MARB is decremented after each data transfer
• If DTSZ = 0, MARB is decremented by 1 after each data transfer
• If DTSZ = 1, MARB is decremented by 2 after each data transfer
Bit 3—Transfer Mode Select (TMS): Selects whether the source or destination is the block area
in block transfer mode.
Bit 3: TMS
0
1
Description
Destination is the block area in block transfer mode
Source is the block area in block transfer mode
(Initial value)
Rev. 3.00 Mar 21, 2006 page 204 of 814
REJ09B0302-0300