HD6473032F16 Datasheet, PDF (45/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 1 Overview
Type
Refresh
controller
Symbol
RFSH
CS3
RD
Pin No.
87
88
70
HWR
71
LWR
72
DMA controller
(DMAC)
DREQ1,
DREQ0
TEND1,
TEND0
9, 8
94, 93
16-bit integrated TCLKD to
timer unit (ITU) TCLKA
TIOCA4 to
TIOCA0
96 to 93
4, 2, 99,
97, 95
TIOCB4 to 5, 3, 100,
TIOCB0
98, 96
TOCXA4 6
TOCXB4 7
I/O
Output
Output
Output
Output
Output
Input
Output
Input
Name and Function
Refresh: Indicates a refresh cycle
Row address strobe RAS: Row address
strobe signal for DRAM connected to area 3
Column address strobe CAS: Column
address strobe signal for DRAM connected
to area 3; used with 2WE DRAM.
Write enable WE: Write enable signal for
DRAM connected to area 3; used with
2CAS DRAM.
Upper write UW: Write enable signal for
DRAM connected to area 3; used with 2WE
DRAM.
Upper column address strobe UCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
Lower write LW: Write enable signal for
DRAM connected to area 3; used with 2WE
DRAM.
Lower column address strobe LCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
DMA request 1 and 0: DMAC activation
requests
Transfer end 1 and 0: These signals
indicate that the DMAC has ended a data
transfer
Clock input D to A: External clock inputs
Input/
output
Input/
output
Output
Output
Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
Input capture/output compare B4 to B0:
GRB4 to GRB0 output compare or input
capture, or PWM output
Output compare XA4: PWM output
Output compare XB4: PWM output
Rev. 3.00 Mar 21, 2006 page 15 of 814
REJ09B0302-0300