HD6473032F16 Datasheet, PDF (595/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

18.5 Register Descriptions
Section 18 ROM
18.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'3FFFF is
entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the
P1 bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a
power-on reset, and in hardware standby mode and software standby mode. Its initial value is H'80
when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash
memory is disabled, a read will return H'00, and writes are invalid.
Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when
FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when
FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1.
Bit
7
6
5
4
3
2
1
0
FWE SWE1 ESU1 PSU1 EV1
PV1
E1
P1
Initial value
1/0
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7: FWE
0
1
Description
When a low level is input to the FWE pin (hardware-protected state)
When a high level is input to the FWE pin
Bit 6—Software Write Enable Bit 1 (SWE1): Enables or disables flash memory programming
and erasing (applicable addresses: H'00000 to H'3FFFF). Set this bit when setting bits 5 to 0, bits 7
to 0 of EBR1, and bits 3 to 0 of EBR2.
Bit 6: SWE1
Description
0
Writes disabled
1
Writes enabled^*
[Setting condition]
When FWE = 1
Note: * Do not execute a SLEEP instruction while the SWE1 bit is set to 1.
(Initial value)
Rev. 3.00 Mar 21, 2006 page 565 of 814
REJ09B0302-0300