HD6473032F16 Datasheet, PDF (366/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the
OVF flag in TSR when OVF is set to 1.
Bit 2: OVIE
0
1
Description
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
(Initial value)
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Bit 1: IMIEB
0
1
Description
IMIB interrupt requested by IMFB is disabled
IMIB interrupt requested by IMFB is enabled
(Initial value)
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt requested by the IMFA flag in TSR when IMFA is set to 1.
Bit 0: IMIEA
0
1
Description
IMIA interrupt requested by IMFA is disabled
IMIA interrupt requested by IMFA is enabled
(Initial value)
Rev. 3.00 Mar 21, 2006 page 336 of 814
REJ09B0302-0300