HD6473032F16 Datasheet, PDF (602/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 18 ROM
Table 18.3 Flash Memory Erase Blocks
Block (Size)
EB0 (4 kbytes)
EB1 (4 kbytes)
EB2 (4 kbytes)
EB3 (4 kbytes)
EB4 (4 kbytes)
EB5 (4 kbytes)
EB6 (4 kbytes)
EB7 (4 kbytes)
EB8 (32 kbytes)
EB9 (64 kbytes)
EB10 (64 kbytes)
EB11 (64 kbytes)
EB12 (64 kbytes)
EB13 (64 kbytes)
EB14 (64 kbytes)
EB15 (64 kbytes)
Addresses
H'000000–H'000FFF
H'001000–H'001FFF
H'002000–H'002FFF
H'003000–H'003FFF
H'004000–H'004FFF
H'005000–H'005FFF
H'006000–H'006FFF
H'007000–H'007FFF
H'008000–H'00FFFF
H'010000–H'01FFFF
H'020000–H'02FFFF
H'030000–H'03FFFF
H'040000–H'04FFFF
H'050000–H'05FFFF
H'060000–H'06FFFF
H'070000–H'07FFFF
18.5.5 RAM Control Register (RAMCR)
RAMCR specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMCR initialized to H'F0 by a power-on reset and in
hardware standby mode. It is not initialized by a manual reset and in software standby mode.
RAMCR settings should be made in user mode or user program mode.
Flash memory area divisions are shown in table 18.4. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
RAMS RAM2 RAM1 RAM0
Initial value
1
1
1
1
0
0
0
0
Read/Write




R/W
R/W
R/W
R/W
Rev. 3.00 Mar 21, 2006 page 572 of 814
REJ09B0302-0300